All processors, microprocessors or central processing units include arithmetic logic units (ALU) to perform calculations involving integers. An ALU will contain a multiplicity of adder circuits or simply adders to perform the arithmetic calculations by summing two binary numbers together. The binary numbers being added will typically contain either 32 bits or 64 bits. Accordingly, adders will typically be of two types of design or architecture, one to handle the summation of 32 bit binary numbers and another to handle the summation of 64 bit binary numbers.
Adders are generally used by the majority of instructions in controlling the operations of a computer system, microprocessor or the like and are performance limiting devices in such systems because they form a core of several critical paths in performing instructions and calculations. A typical adder circuit can include over 500 logic gates and will generate a carry for every two bits summed together for two 64 bit or 32 bit binary numbers. Accordingly, 64 summations and carries are generated in parallel operations. While the time period during which these arithmetic operations are performed is extremely fast, a simpler architecture with fewer gates would perform fewer operations in a much shorter time period. A larger number of logic gates and a longer period of time to perform operations will also result in more power consumption.
Additionally, the more complex adder circuit with hundreds of logic gates requires additional and more complex wiring to interconnect the hundreds of gates and will also occupy a considerable area or real estate on a semiconductor chip.
Another issue with some adders that use a multiplexer to select between different conditional sums or conditional carries is that a conditional sum or conditional carry input to the multiplexer may be erroneously discharged that could result in a later arriving true conditional sum input or true conditional carry input to the multiplexer not being evaluated correctly.
Accordingly, for the reason stated above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for a robust, high performance adder with a simplified architecture, that occupies less area on a semiconductor chip and that operates faster and with less power consumption and is not subject to incorrect evaluation of conditional sums and conditional carries.